1. Field of the Invention
The present invention generally relates to semiconductor devices and manufacturing methods for the devices and particularly, to a Lateral Double Diffusion Metal Oxide Semiconductor (LDMOS) device.
2. Description of the Related Art
High-voltage LDMOSes are often utilized in high-votage power integrated circuits to meet requirements of high voltage withstanding, power controlling, and so on. LDMOSes are also commonly used in RF power circuits. As compared to normal transistors, LDMOSes have significant advantages in key characteristics, such as gain, linearity, switch performance, heat dissipation, and reduced stages. Presently, LDMOSes are widely used due to their good compatibility with CMOS processes.
FIG. 11 shows a schematic diagram of a LDMOS of the prior art. The LDMOS shown has a lightly doped N-type drift region 210(N−) on a substrate 200, and a deeply doped N-type drain region 280 (N+) located in the drift region 210. The LDNMOS has a p-well 220 on the substrate 200, and a deeply doped source region 290 disposed in the p-well 220. A gate dielectric layer 270 is located below a gate 300. As to the LDMOS device, the source 290-to-drain 280 region can endure a high voltage since the N-drift region 210 has a very high resistance. Thereby, as shown by the arrow 295 in FIG. 11, the drain 280 and gate 300 have an overlap region where the drain resistance is very small, the high voltage at the drain 280 is directly applied on the overlap region of the drain 280 and gate 300 without voltage dividing of a high resistance region, and consequently, gate oxide layer breaking down may occur in the drain-gate overlap region, which will cause device failure.
In existing LDMOS devices, it is possible to increase the thickness of the gate dielectric layer 270 to raise the break-down voltage of the drain-gate overlap region. However, a thicker gate dielectric layer 270 may degrade the device performance.